The present invention relates to the field of electronic design automation (EDA). More specifically, the present invention relates to the verification of integrated circuit designs using computer aided design (CAD) tools.
Rapid growth in the complexity of modern electronic circuits has forced electronic circuit designers to rely upon computer programs to assist and automate most steps of the integrated circuit design process. Typical circuits today contain hundreds of thousands or millions of individual pieces or xe2x80x9ccells.xe2x80x9d These designs are much too large for a circuit designer or even an engineering team of designers to manage effectively manually. To automate the design and fabrication of integrated circuit devices, the field of electronic design automation (EDA) has been developed which uses computer aided design (CAD) tools and systems.
Typically, CAD tools function in part by decomposing the overall desired behavior of the integrated circuit into simpler functions which can be represented as functional cells by the CAD tool. The CAD tool generates netlists including cells, logic gates and connections between them which perform the desired circuit behavior. Netlists can represent the integrated circuit in different levels of abstraction depending on the CAD function being performed, such as the behavior level, the structural level and the gate level. The behavioral level hardware description language (HDL) netlist is typically the starting level for CAD tools because the HDL description file describes the behavior of the integrated circuit. The gate level HDL netlist is usually the level at which the functional verification of the integrated circuit is performed.
Achieving the desired degree of reliability in a complex integrated circuit thus depends upon being able to analyze the circuit""s HDL design early in the design process. In so doing, the consequences of design choices and trade-offs can be explored and tested prior to design implementation, and potentially disastrous flaws can be detected and remedied while their cost of repair is still relatively inexpensive. For example, detecting a flaw in a microprocessor design prior to its mass fabrication is much more desirable and much more economical than correcting the consequences of the flaw after the microprocessor has been deployed in systems throughout the world. Such testing is commonly referred to as design verification. Computer engineers and other designers of complex systems use numerous EDA tools to aid in design verification and debugging.
The extensive use of EDA tools have given rise to modern integrated circuit devices having greater and greater densities. The higher densities are greatly increasing the costs associated with verifying the designs of such devices. The problem of performing design verification on complex integrated circuit devices includes problems related to the devising of sufficiently accurate tests that adequately ensure the complete functionality of the devices. For example, as the complexity of an integrated circuit design increases (e.g., the total number of logic gates increases and the total number of storage elements increases), the total number of possible states of the design increases. The increasing number of possible states causes a geometric increase in the amount of processing power (e.g., CPU cycles) required to run the design verification EDA tools (e.g., simulators, ATPG programs, etc.).
To verify a given complex integrated circuit design, the designer will use an EDA simulation tool to examine the possible states of a representative simulation of the integrated circuit (e.g., a state machine, etc.) and examine the transitions between the states to determine whether the circuit can achieve all of its xe2x80x9cdesired statesxe2x80x9d and determine whether the circuit successfully avoids all xe2x80x9cillegal statesxe2x80x9d. A desired state may represent, for example, correctly calculating a desired result. An illegal state may represent, for example, and error condition which results in system malfunction.
This design verification involves the simulation of those components within the design that store state information. Each memory element within the integrated circuit design stores state information, and hence, needs to be accurately simulated. The goal of the design verification is to simulate the memory elements to compute the set of all reachable states from an initial state of a integrated circuit design, and to use this information to verify the behavior and internal configuration of the design.
There is a problem, however, when the size of the integrated circuit design becomes quite large. Large complex integrated circuit designs, including a large number of memory elements, can result in a simulation (e.g., a finite state machine) having an unmanageably large number of possible states. For example a modern microprocessor often processes information in data words of up to 64 bits in one cycle. This results in a very large number of inputs and outputs per state, and a very large number of state transitions, and thus an extremely large number of possible states, requiring the accurate simulation of each memory element. The large number of memory elements require an very large amount of processor time to update within the simulation.
Thus, what is required is a more efficient method and system for design verification for complex integrated circuits having a very large number of possible states. What is required is an efficient method and system for simulating an integrated circuit having a large number of memory elements. What is required is a system which can efficiently process and update the memory elements of a simulation of an integrated circuit. The present invention provides a novel solution to the above requirements.
The present invention provides an efficient method and system for design verification for complex integrated circuits having a very large number of possible states. The present invention provides an efficient method and system for simulating an integrated circuit having a large number of memory elements. Additionally, the present invention provides a system which can efficiently process and update the memory elements of a simulation of an integrated circuit.
In one embodiment, the present invention is implemented as a software based EDA process for efficiently simulating memory structures of a sequential circuit for design verification of the sequential circuit. The process is implemented within the context of an EDA computer system used for simulating the operation of complex integrated circuit devices. The process includes accessing an HDL netlist description of the sequential circuit. In this embodiment, a gate level netlist description is used for the verification. Memory elements included within the netlist description are identified. For these memory elements, inputs to the memory elements and outputs from the memory elements are identified. Using this information, the memory elements are grouped into at least one group of functionally related memory elements. Subsequently, the memory elements of the one or more groups are collectively addressed as a group. Similarly, data for the memory elements of the one or more groups are collectively written as a group. Once written, the data is coupled to circuit elements within the description that are coupled to the outputs of the memory elements such that the memory elements are efficiently.simulated group-wise, as opposed being simulated individually.
In so doing, a more efficient process and system for design verification for sequential circuits is implemented. For those circuits having a very large number of memory elements, the simulation process of the present invention provides a significant savings in the amount of processing time (e.g., CPU cycles) required to run the simulation. Accordingly, using the simulation process of the present invention, even those circuits having a very large number of possible states can be simulated, and the design of the circuits can be accurately verified within reasonable time constraints.